Timing closure for Shrike Lite

General
1

Hello everyone,

I am not really sure how to post but here goes; I come from an FPGA background, and I am concerned that the timing has not been met in the FPGA. I tried putting a sdc file with a create_clock constraint, but the tool is not recognizing the constraint.

Following is the snippet for the create clock constraint:

create_clock -name sys_clk -period 20.0 -waveform {0 5.0} [get_ports clk]

My top module is as shown below:

(* top *) module blink(
  (* iopad_external_pin, clkbuf_inhibit *) input clk,
  (* iopad_external_pin *) output LED,
  (* iopad_external_pin *) output LED_en,
  (* iopad_external_pin *) output clk_en
  );

Any help is appreciated. The design works; I just want to understand why the timing is not met. I am using “Go Configure Software Hub” version 6.53.

2

can you share the logs for us to check

The constrains looks fine

3

Hi noddy,

Attaching the logs:
build.zip (161.7 KB)

Let me know if you need any other logs.